Audio amplifier

ABSTRACT

In an audio amplifier having a D-class power amplifier, a noise upon muting is suppressed. A sampling rate converter circuit for sampling rate converting a digital audio signal into a digital audio signal, and a ΔΣ modulation circuit for re-quantizing the digital audio signal into a bit-reduced digital audio signal are provided. Further, a PWM modulation circuit for converting the digital audio signal into a PWM signal, and a D-class power amplifier to which the PWM signal are supplied. Still further, a dither signal forming circuit for superimposing a dither signal SDI on the digital audio signal, and a forming circuit for forming a muting signal SDET are provided. Upon muting, an input side of the sampling rate converter circuit is stopped by the muting signal SDET.

TECHNICAL FIELD

This invention relates to an audio amplifier.

BACKGROUND ART

In an audio amplifier, if a power amplifier of a final stage isconfigured with a so-called D-class amplifier, a whole is able to bedigitized, and is able to be configured as a digital audio amplifier.

FIG. 3 shows one example of such digital audio amplifier. Namely, adigital audio signal S11 is supplied to an over-sampling circuit 12 froman input terminal 11, a sampling frequency thereof is over-sampled to bea digital signal S12 of 8 times, this digital signal S12 is supplied toa ΔΣ modulation circuit 14 through a variable attenuator circuit 13 forvolume control, and is re-quantized to be bit-reduced digital signalS14. Further, this digital signal S14 is supplied to a PWM modulationcircuit 15, and converted to a PWM signal S15, then this PWM signal S15is supplied to a power amplifier 16 operating in D-class.

This power amplifier 16 is configured with a switching circuit for poweramplifying by switching a power source voltage in accordance with thePWM signal S15, and a low pass filter for outputting a D/A converted andpower amplified analog audio signal by smoothing the switching output.Further, by the power amplifier 16, the power amplified audio signal issupplied to a speaker 30 through an output terminal 17.

Further, in a system controller (not illustrated), a volume controlsignal SVOL is formed, and this signal SVOL is supplied to the variableattenuator circuit 13 as a control signal. Accordingly, when a switchfor the volume control is operated, an attenuation level of the variableattenuator circuit 13 is changed, and a volume of a reproduced soundoutputted from the speaker 30 is changed.

Further, in this case, the ΔΣ modulation circuit 14 includes a feedbackloop for a quantizing error, so that even if a content of the digitalsignal S12 supplied from the variable attenuator circuit 13 to the ΔΣmodulation circuit 14 is zero, a digital signal S14 having somethingvalue is accordingly outputted from the ΔΣ modulation circuit 14, andthe digital signal S14 is accordingly outputted from the speaker 30 as anoise sound having a specified frequency.

Consequently, in a dither signal forming circuit 18, a dither signal SDIof a minute level is formed, this dither signal SDI is supplied to theΔΣ modulation circuit 14, and is superimposed on the digital signal S12upon re-quantization. Accordingly, even in a case where the content ofthe digital signal S12 outputted from the variable attenuator circuit 13is zero, an actual content of the ΔΣ modulation circuit 15 does notbecome zero, so that it is suppressed to output the noise sound.

Further, in a case when the digital signal S11 to be supplied to theinput terminal 11 is switched or disconnected by the switching of thesource devices supplying the digital signal S11, the synchronization ofthe digital signal S11 is temporary disturbed, and this disturbance ofsynchronization is accordingly outputted from the speaker 30 as thenoise sound.

For the sake, the digital signal S11 supplied to the input terminal 11is supplied to an asynchronous detection circuit 19, and a disturbanceof synchronization of the digital signal S11 is detected. Further, thisdetection signal SDET is supplied to the circuits 12 to 14 as a mutingsignal, and when the synchronization of the digital signal S11 isdisturbed, the contents of the signals S12 and S14 are set to be zero,and as the result, the reproduced sound outputted from the speaker 30 ismuted.

The above is one example of an audio amplifier where the power amplifier17 in the final stage is configured with a D-class amplifier (SeeJapanese Laid-open Patent Application OP2002-158543, for example).

By the way, in case of the audio amplifier as shown in FIG. 3, when amuting is performed by the detection signal SDET of the asynchronousdetection circuit 19, not only the digital signal S12 is muted, but alsothe dither signal SDI is simultaneously muted in the ΔΣ modulationcircuit 14. Accordingly, the dither signal SDI is abruptly cutoff uponmuting, and a noise signal is generated by this abrupt cutoff, so thatthis is outputted from the speaker 30 as a noise sound.

Further, though the dither signal SDI has a minute level, thepresence/absence of the dither signal SDI is able to be recognized as adifference in a noise level. Therefore, when the muting is set to be on,the noise level changes because the dither signal SDI is muted, but in acase where the content of the input digital signal S11 is zero (or aminute level), the change in the noise level is recognized, and thiscauses uncomfortable feeling.

This invention is to solve the above problems.

DISCLOSURE OF THE INVENTION

According to the present invention, an audio amplifier is configured toinclude, for example, a sampling rate converter circuit for performing asampling rate conversion of a first digital audio signal with a firstclock synchronized thereto and a second clock having a predeterminedfrequency into a second digital audio signal synchronized with thesecond clock, a ΔΣ modulation circuit for re-quantizing the seconddigital audio signal into a third digital audio signal having reducednumber of bits, a PWM modulation circuit for converting the thirddigital audio signal into a PWM signal, a D-class power amplifier to besupplied the PWM signal outputted from the PWM modulation circuit, adither signal forming circuit for superimposing a dither signal on thethird digital audio signal by supplying the dither signal to the ΔΣmodulation circuit, and a muting signal forming circuit, wherein aninput side of the sampling rate converter circuit is stopped by a mutingsignal upon muting.

Accordingly, the dither signal is continuously supplied to the ΔΣmodulation circuit even during muting, and the digital audio signalincluding the dither signal is supplied to the D-class power amplifierafter converting into the PWM signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system chart designating one mode of the present invention.

FIG. 2 is a chart for describing the present invention.

FIG. 3 is a system chart for describing the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows one example of a digital audio amplifier 10 according tothe present invention, and a digital audio signal S11 is supplied to anover-sampling circuit 12 through an input terminal 11. Further, thedigital signal S11 from the input terminal 11 is supplied to a PLL 21, aclock SPLL synchronized with the digital signal S11 and having afrequency of n times of its sampling frequency is formed, and thusgenerated clock SPLL is supplied to the over-sampling circuit 12 as aclock for over-sampling. In this case, the magnification n of theover-sampling is set to be a value as shown in FIG. 2 corresponding tothe sampling frequency of the digital signal S11.

Thus, in the over-sampling circuit 12, the digital signal S11 suppliedthereto is over-sampled to a digital signal S12 synchronized with thesignal S11, and having a frequency of n times the sampling frequency.

And, this digital signal S12 is supplied to the sampling rate convertercircuit 23 as a conversion input. Further, the clock SPLL from the PLL21 is supplied to the sampling rate converter circuit 23 as a clock forconversion input side.

Further, the clock forming circuit 22 is configured with a crystaloscillation circuit, and a dividing circuit, and a clock SGEN having afrequency of 49.152 MHz (=48 kHz×1024) with a stable frequency and aphase is derived from this clock forming circuit 22. Then, this clockSGEN is supplied to the sampling rate converter circuit 23 as a clock ofconversion output side. Thus, in the sampling rate converter circuit 23,the digital signal S12 supplied thereto is converted into a digitalsignal S23 having a sampling frequency which is a frequency of 384 kHz(=48 kHz×8), for example, with a stable frequency and a phase.

Then, the sampling rate converted digital signal S23 is supplied to thevariable attenuator circuit 13 for the volume control, the level thereofis controlled by the control signal SVOL from the system controller (notillustrated), the level controlled digital signal S12 is supplied to theΔΣ modulation circuit 14, and is re-quantized into a bit-reduced digitalsignal S14. By the way, in the dither signal forming circuit 18, thedither signal SDI of a minute level is formed at this time, and thisdither signal SDI is superimposed on the digital signal S23 to besupplied to the ΔΣ modulation circuit 14.

Then, the digital signal S14 re-quantized by the ΔΣ modulation circuit14 is supplied to the PWM modulation circuit 15, and is converted into aPWM signal S15. This PWM signal S15 is then supplied to the poweramplifier 16 operating in D class, and power amplified, and after that,thus amplified output is supplied to the speaker 30 through the outputterminal 17.

At this time, the clock SGEN from the forming circuit 22 is supplied tothe circuits 13 to 15, and 18 as their clocks. Accordingly, the outputside of the sampling rate converter circuit 23 and the circuits 13 to15, and 18 are to be operated in synchronism with the clock SGEN.

Further, the digital signal S11 supplied to the input terminal 11 issupplied to the asynchronous detection circuit 19, also the clock havinga frequency equal to the sampling frequency of the input digital signalS11 and synchronized thereto is derived from the PLL 21, this clock issupplied to the asynchronous detection circuit 19, and a disturbance ofthe synchronization of the digital signal S11 supplied to the inputterminal 11 is detected.

Then, the detection signal SDET is supplied to the over-sampling circuit12, an input side of the sampling rate converter circuit 23, and thevariable attenuator circuit 13 as a muting signal, and when asynchronization of the digital signal S11 is disturbed, the content ofthe signal S12 is set to be zero, and also the operation of the inputside in the sampling rate converter circuit 23 is stopped.

According to the above-mentioned configuration, the digital audio signalS11 supplied to the input terminal 11, in spite of its samplingfrequency, the sampling frequency is converted its sampling rate intothe digital signal having a sampling frequency of 384 kHz by thesampling rate converter circuit 23, and after that, it is poweramplified after converted into the PWM signal S15, then supplied to thespeaker 30.

Further, as a result of switching or disconnecting the digital signalS11 to be supplied to the input terminal 11 by the switching of thesource devices supplying the digital signal S11, the synchronization ofthe digital signal S11 is temporary disturbed, and this disturbance ofsynchronization is detected by the asynchronous detection circuit 19,and by the detection signal SDET, the over-sampling circuit 12 and theinput side of the sampling rate converter circuit 23 are stopped.Accordingly, the digital signal S12 is to be shut out during an intervalof the detection signal SDET.

However, even the operation of the input side in the sampling rateconverter circuit 23 during the interval of the detection signal SDET isstopped, the digital signal S23 is continuously outputted from thesampling rate converter circuit 23, because the output side thereof issupplied with the clock SGEN, and the operation is continuous.

However in this case, as the operation of the input side in the samplingrate converter circuit 23 is stopped and the detection signal SDET isalso supplied to the variable attenuator circuit 13, the content of thedigital signal S23 outputted from the variable attenuator circuit 13 iszero.

Then, such digital signal S23 is supplied to the ΔΣ modulation circuit14, and the detection signal SDET is not supplied to the ΔΣ modulationcircuit 14, during the interval of the detection signal SDET, thedigital signal S14 the content of which is zero is outputted from the ΔΣmodulation circuit 14, and this digital signal S14 is supplied to thePWM modulation circuit 15. Accordingly, during the interval of thedetection signal SDET, a muting is activated to the input audio signalS11. That is, the interval of the detection signal SDET is the mutinginterval.

As described above, the digital audio amplifier shown in FIG. 1, themuting is performed, however, even during the muting interval, thedither signal SDI is supplied to the ΔΣ modulation circuit 14, andaccordingly, even if the content of the digital signal S23 suppliedthereto is zero, it never happens to output from the ΔΣ modulationcircuit 14 the signal components which become a noise sound of aparticular frequency.

Further, even during the muting interval, the dither signal SDI issupplied to the ΔΣ modulation circuit 14, the noise levels become equalbetween when the muting is off and when the muting is on. Accordingly,in a case when the content of the input digital signal S11 is zero (or,a minute level), if a muting is activated, there is no fear of beingrecognized the change in the noise level and uncomfortable feeling.

Further, when changing from a state where the muting is off to a statewhere the muting is on, and when changing from a state where the mutingis on to a state where the muting is off, the dither signal SDI isalways continuing, so that there is no fear of generating noise signals,and also there is no fear of outputting a noise sound from the speaker30.

(List of Abbreviations Used in this Specification)

-   -   D/A Digital to Analog    -   PLL: Phase Locked Loop    -   PWM: Pulse Width Modulation

INDUSTRIAL APPLICABILITY

According to the present invention, even if a muting is on when thecontent of the input digital audio signal is zero, or a minute level,there is no fear of uncomfortable feeling due to the recognition of thechange in the noise level. Further, when the muting is made on from themuting off state, or when the muting is released from the muting onstate, there is no fear of generating noise signals, and also there isno fear of outputting a noise sound from the speaker.

1. An audio amplifier comprising: a sampling rate converter circuit for converting a sampling rate of a first digital audio signal with a first clock synchronized thereto and with a second clock having a stable and predetermined frequency into a second digital audio signal synchronized with the second clock; a ΔΣ modulation circuit for re-quantizing the second digital audio signal into a bit-reduced third digital audio signal; a PWM modulation circuit for converting the third digital audio signal to a PWM signal; a D-class power amplifier supplied with the PWM signal outputted from the PWM modulation circuit; a dither signal forming circuit for superimposing a dither signal on the third digital audio signal by supplying the dither signal to the ΔΣ modulation circuit; and a muting signal forming circuit; wherein an input side of the sampling rate converter circuit is stopped by the muting signal upon muting.
 2. The audio amplifier as cited in claim 1, wherein when the first digital audio signal becomes a asynchronous state, the muting signal forming circuit is set to be a asynchronous detection circuit for detecting it, and the detection signal of this asynchronous detection circuit is set to be the muting signal. 